With silicon clock scaling largely dead thanks to the laws of physics, computer scientists and chip designers have had to search for performance improvements in other areas -- typically by improving ...

Part 1: A look at the impact of communication across multiple processors on an SoC and how to to make that more efficient. Managing how the processors in an SoC talk to one another is no small feat, ...

System-Level Design sat down to discuss coherency with Mirit Fromovich, principal solutions engineer at Cadence; Drew Wingard, CTO of Sonics; Mike Gianfagna, vice president of marketing at Atrenta, ...

In addition to the cache-coherence protocol discussed here, Sun already used formal verification successfully to verify other protocol-related problems. Architecture-level protocol verification is a ...

One of the key challenges in chip multi-processing is to provide a programming model that manages cache coherency in a transparent and efficient way. A large number of applications designed for ...

If multiple devices, such as the CPU and peripherals, access the same cacheable memory region, cache and memory can become incoherent. This is illustrated in Figure 7. Suppose the CPU accesses a ...

The US Court of Appeals for the Federal Circuit, addressing the issue of whether certain factual and legal conclusions relating to obviousness were supported by substantial evidence, held that the ...