Semiconductor Engineering

Writing Reusable UPF For RTL And Gate-Level Low Power Verification

The Unified Power Format (UPF) is used to specify the power intent of a design. Once written, the UPF file is applied at every stage of the design cycle — starting with the RTL, then the gate-level, ...
Design-Reuse

Avery Design Systems Unveils SimXACT for Elimination of X Pessimism Issues in Gate-Level ...

ANDOVER, Mass.-- March 23, 2012--Avery Design Systems Inc., an innovator in functional verification productivity solutions, today announced availability of its revolutionary X verification solution, ...
EDN

Reuse UVM RTL verification tests for gate level simulation

When we verify a System on Chip (SoC) that embeds microprocessors with several digital peripherals, and possibly analog blocks as well, we want to check all the implemented features and possible ...
Electronic Design

Instant "Replay" Comes To Timing Simulation

Many designers continue to perform timing simulation for gate-level designs. Through an add-on module for its Siloti Visibility Enhancement software, Novas Software now brings timing-accurate ...
EDN

Synopsys pulls VHDL and Verilog together and boosts speed

Synopsys has reworked a number of routines in its VCS hardware simulation tool in an attempt to improve performance at both the gate and RTL level to the point where the company reckons it now has the ...