EDN

Link for Modelsim 2 adds direct Verilog support

SAN FRANCISCO — The MathWorks Monday (July 24) announced the availability of Link for ModelSim 2, said to enhance the use of model-based design for hardware verification by offering full Verilog and ...
Design-Reuse

Hitachi Endorses Model Technology ModelSim for Verilog Simulation

PORTLAND, Ore.--(BUSINESS WIRE)--Oct. 3, 2001--Model Technology(TM), a Mentor Graphics company, today announced that the ModelSim® hardware description language (HDL) simulator has received Verilog ...
Ars Technica

Open Source VHDL (or similar) CPU Simulation Software

Hey all, my last semester of college we had to develop the microarchitecture for a RISC processor. My group was ultimately unsuccessful (our L2 cache had some serious issues), but I wouldn't mind ...
Design-Reuse

TransEDA Again Accelerates System-On-Chip Verification with New Version of its Verification Navigator Environment

Los Gatos, Calif. - January 21, 2002 - TransEDA® PLC, the leader in ready-to-use verification solutions, announced a new version of its Verification Navigator® Integrated Design Verification ...
EDN

Consultant creates low-end mixed-signal simulator

Santa Cruz, Calif. – In the middle of a tough design project in 2002, consultant Brendan Graham needed an inexpensive mixed-signal simulation tool. He couldn't find one, so his company, µSysIntegral, ...
Electronic Design

Verilog Simulator Adds Full-Featured Coverage Analysis And A C/C++ Interface

The latest VCS Verilog simulator from Synopsys contains built-in comprehensive coverage analysis. With it, design teams using VCS 6.0.1 can determine their verification quality before tapeout.