NanoTime is a next-generation transistor-level static timing analysis solution that provides concurrent timing and signal integrity analysis for ASIC designs. Its performance and capacity allow ...

To support the growing demand for statistical static timing analysis (SSTA) tools in the design and verification of highly-complex SoCs, Santa Clara, Calif.-based startup Altos Design Automation Inc.

They said it couldn't be done, but Synopsys has imbued its PrimeTime 2009.12 static timing analyzer with the ability to run in multi-threaded and distributed multicore modes. Synopsys continues to ...

SAN JOSE, Calif.--(BUSINESS WIRE)--Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced the Tempus ™ Power Integrity Solution, the industry’s first comprehensive static timing/signal integrity ...

In a perfect world, fabrication of silicon ICs would be a perfectly predictable process. Not only would every chip be absolutely identical, but there would be no variations from wafer to wafer, or lot ...

About five years ago if you listened to the marketing messages in the EDA industry, you would have thought it would be impossible to produce chips without statistical static timing analysis (SSTA).

Accurate static timing analysis is one of the most important steps in the development of advanced node semiconductor devices. Performance numbers are included in chip and system specifications from ...

(click to enlarge) The results page of a static analysis tool. In this example, the tool found 1400 uninitialized variables in less than 20 minutes. Recently the FDA software forensics lab announced ...