IEEE

HaVen: Hallucination-Mitigated LLM for Verilog Code Generation Aligned with HDL Engineers

Abstract: Recently, the use of large language models (LLMs) for Verilog code generation has attracted great research interest to enable hardware design automation. However, previous works have shown a ...
IEEE

Graph-Based Representation of Verilog HDL: Python-Based Control and Data Flow Graph Generation

Abstract: This paper proposes an automatic framework for controlled data flow graph (CDFG) generation from verilog designs, where the generated CDFGs can be applied to visualization, formal ...